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Full Table of Contents

Contents
About This Guide
Who This Guide Is For
What the Book Contains
Other Useful Books
1. - Real-Time Programs
Defining Real-Time Programs
Major Types of Real-Time Programs
Simulators
Requirements on Simulators
Frame Rate
Transport Delay
Aircraft Simulators
Ground Vehicle Simulators
Plant Control Simulators
Virtual Reality Simulators
Hardware-in-the-loop (HITL) Simulators
Data Collection Systems
Requirements on Data Collection Systems
Achieving High Transfer Rates to Devices
Achieving High Transfer Rates to Disk
Real-Time Programming Languages
2. - Basic Features of the CHALLENGE and IRIX(TM) Architectures
Multiprocessor Architecture
CPUs, Memory, and the System Bus
Concurrent Execution
Memory Hierarchy
Cache Coherency Updates
Virtual Memory
Translation Lookaside Buffer Updates
Device Interrupts
VME Interrupts
Interrupt Latency
Interrupt Response Time
Processor Arrays
Process Management
Process Composition
Process Creation
Normal Process Creation With fork()
Address Space Replacement With exec()
Lightweight Process Creation With sproc()
Process Scheduling
I/O Scheduling
Disk I/O
VME Bus I/O
Other I/O
Asynchronous I/O
3. - How IRIX(TM) and REACT/Pro(TM) Support RealTime Programs
Kernel Facilities for Real-Time Programs
Kernel Optimizations
Special Scheduling Disciplines
Nondegrading Priorities
Deadline Scheduling
Gang Scheduling
Processor Sets
Locking Virtual Memory
Mapping Processes and CPUs
Controlling Interrupt Distribution
REACT/Pro Frame Scheduler
How Frames Are Defined
Advantages of the Frame Scheduler
Designing With the Frame Scheduler
Interprocess Communication
Shared Memory Segments
IRIX Shared Memory Arenas
SVR4-Compatible Shared Memory
Semaphores
IRIX Semaphores
SVR4-Compatible Semaphores
Locks
Barriers
Mutual Exclusion Primitives
Signals
Signal Latency
Timers and Clocks
Timer Interrupts (Itimers)
BSD Itimers
POSIX Timers
Timestamps
Time of Day Timestamp
Hardware Cycle Counter
Interchassis Communication
Socket Programming
Message-Passing Interface (MPI)
Reflective Shared Memory
External Interrupts
4. - Managing Virtual Memory in a RealTime Program
Defining the Address Space
Address Space Boundaries
Page Numbers and Offsets
Address Definition
Address Space Limits
Page Validation
Read-Only Pages
Copy-on-Write Pages
Interrogating the Memory System
Locking Pages in Memory
Locking Functions
Locking Program Text and Data
Locking Mapped Files Into Memory
Reducing Cache Misses
Locality of Reference
Cache Mapping in Challenge/Onyx
Multiprocessor Cache Conflicts
Detecting Cache Problems
5. - Managing Time and Time Intervals
Using Interval Timers
Timed Pauses
POSIX Timer Support
BSD Timer Support
Using an Itimer
Time Data Structures
Time Signal Latency
How Timers Are Managed
Timer Management in Challenge, Onyx, and POWER-Challenge
Timer Management Without a Clock Comparator
Using Short Timer Intervals
Fast Timers With a Clock Comparator
Fast Timers Without a Clock Comparator
Selecting the fasthz Value
Which CPU Handles Timer Interrupts
Using Timestamps
Using the Time of Day
Using BSD gettimeofday()
Using POSIX clock_gettime()
Using the Cycle Counter
Comparing the Timestamps
6. - Controlling CPU Workload
Using Priorities and Scheduling Queues
Scheduling Concepts
Tick Interrupts
Time Slices
Priorities
Aging Priorities
Scheduler Queues
Setting a Nondegrading Batch Priority
Setting a Nondegrading Real-Time Priority
Understanding Affinity Scheduling
Using Gang Scheduling
Using Deadline Scheduling
Changing the Time Slice Duration
Using Processor Sets
Assigning a Process to a Processor Set
Assigning a Processor Set to a Queue
Assigning a Discipline to a Processor Set
Processor Set Contradictions
Minimizing Overhead Work
Assigning the Clock Processor
Assigning the fasthz Processor
Unavoidable Timer Interrupts
Isolating a CPU From Sprayed Interrupts
Assigning Interrupts to CPUs
Understanding the Vertical Sync Interrupt
Restricting a CPU From Scheduled Work
Assigning Work to a Restricted CPU
Isolating a CPU From TLB Interrupts
Isolating a CPU When Performer(TM) Is Used
Making a CPU Nonpreemptive
Minimizing Interrupt Response Time
Maximum Response Time Guarantee
Components of Interrupt Response Time
Hardware Latency
Software Latency
Kernel Critical Sections
Service Time for Other Devices
Device Service Time
Dispatch Cycle
Adjust Scheduler Queue
Switch Processes
Mode Switch
Minimal Interrupt Response Time
7. - Using the Frame Scheduler
Frame Scheduler Concepts
Frame Scheduler Basics
Frame Scheduling
The FRS Control Process
The Frame Scheduler API
Library Interface for C Programs
System Call Interface for Fortran and Ada
Process Execution
Scheduling Within a Minor Frame
Scheduler Flags frs_run and frs_yield
Detecting Overrun and Underrun
Estimating Available Time
Using Multiple Synchronized Schedulers
Starting a Single Scheduler
Starting Multiple Schedulers
Pausing Frame Schedulers
Managing Activity Processes
Selecting a Time Base
On-Chip Timer Interrupt
High-Resolution Timer
Vertical Sync Interrupt
External Interrupts
Device Driver Interrupt
Software Interrupt
Using the Scheduling Disciplines
Realtime Discipline
Background Discipline
Underrunable Discipline
Overrunnable Discipline
Continuable Discipline
Using Multiple Consecutive Minor Frames
Preparing the System
Implementing a Single Frame Scheduler
Implementing Synchronized Schedulers
Syncronized Scheduler Concepts
Synchronized Schedulers: the Sync-Master Process
Synchronized Schedulers: Sync-Slave Processes
Handling Frame Scheduler Exceptions
Exception Types
Exception Handling Policies
Injecting a Repeat Frame
Extending the Current Frame
Dealing With Multiple Exceptions
Setting Exception Policies
Querying Counts of Exceptions
Using Signals Under the Frame Scheduler
Signal Delivery and Latency
Handling Signals in the FRS Controller
Handling Signals in an Activity Process
Setting Frame Scheduler Signals
Using Timers with the Frame Scheduler
The Frame Scheduler Device Driver Interface
Device Driver Overview
Exporting the Initialization and Termination Functions
Frame Scheduler Initialization Function
Frame Scheduler Termination Function
Generating Interrupts
8. - Optimizing Disk I/O for a Real-Time Program
Memory-Mapped I/O
Asynchronous I/O
Conventional Synchronous I/O
Synchronous Input
Synchronous Output
Asynchronous I/O Basics
Two Implementation Versions
Asynchronous I/O Functions
Asynchronous I/O Control Block
Initializing Asynchronous I/O
Implicit Initialization
Initializing with aio_sgi_init()
When to Initialize
Scheduling Asynchronous I/O
Assuring Data Integrity
Checking the Progress of Asynchronous Requests
Polling for Status
Checking for Completion
Establishing a Completion Signal
Establishing a Callback Function
Holding Callbacks Temporarily
Multiple Operations to One File
Synchronous Writing and Direct Writing
Using Synchronous Writing
Using Direct I/O
Performance Comparison
Using a Delayed System Buffer Flush
Guaranteed-Rate I/O
Guaranteed-Rate I/O Basics
Creating a Real-time File
Requesting a Guarantee
Releasing a Guarantee
Sharing Access to Guaranteed Files
Hard Guarantees
Soft Guarantees
Video On Demand (VOD) Guarantees
9. - Managing Device Interactions
Device Drivers
How Devices Are Defined
How Devices Are Used
Device Driver Entry Points
Taking Control of Devices
SCSI Devices
SCSI Hardware on CHALLENGE and Onyx Systems
SCSI Adapter Support
System Disk Device Driver
System Tape Device Driver
Generic SCSI Device Driver
CD-ROM and DAT Audio Libraries
The VME Bus
CHALLENGE Hardware Nomenclature
VME Bus Attachments
VME Address Space Mapping
PIO Address Space Mapping
DMA Mapping
Program Access to the VME Bus
PIO Access
User-Level Interrupt Handling
DMA Access to Master Devices
DMA Engine Access to Slave Devices
Serial Ports
External Interrupts
A. - Sample Programs
Mapping and Reading the Cycle Counter
Testing Cycle Counter Precision.
Reading the Cycle Counter
Getting the Time of Day Stamp
Interprocess Communication
Probing the Address Space
Deadline Scheduling Subroutines
Asynchronous I/O Example
Guaranteed-Rate Request
Frame Scheduler Examples
Basic Example
Real-Time Application Specification
Frame Scheduler Design
Example of Scheduling Separate Programs
Examples of Multiple Synchronized Schedulers
Example of Device Driver
Examples of a 60 Hz Frame Rate
Example of Managing Lightweight Processes
Glossary
Index
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